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Digital signal processing questions
Send a voltage a hundred miles and noise ruins it on the way. Send the same information as ones and zeros and a repeater partway along can rebuild it at its original levels. Logic gates then combine to add or compare binary inputs, and flip-flops store one bit so a circuit can count.
17 original questions · 50 marks · the digital signal processing notes · Electronics
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Explain why a digital signal is far less affected by noise on a long cable than an analogue signal carrying the same information.
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An analogue signal carries its information in its exact shape, so any noise added on the way becomes part of the signal and cannot afterwards be told apart from it (1). A digital signal has only two meaningful levels, and the receiver asks only whether each pulse is above or below a threshold, so noise smaller than half a logic level leaves the decision unchanged (1). Answering that digital signals are 'sent at higher power' is the standard error, and it is wrong twice over: digital links usually use less power.State the difference between regenerating a digital signal and amplifying an analogue one.
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An amplifier multiplies whatever arrives, so it boosts the accumulated noise along with the signal and every leg of the journey leaves the signal permanently worse (1). A regenerator decides whether each incoming pulse is a 0 or a 1 and issues a brand-new, full-height, noise-free pulse, discarding the noise collected so far entirely (1). Saying a repeater 'amplifies the digital signal' is the standard error; it replaces it.Write out the truth table of an EOR gate, and state in one sentence what it does.
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A = 0 B = 0 → 0
A = 0 B = 1 → 1
A = 1 B = 0 → 1
A = 1 B = 1 → 0
The output is 1 when the inputs differ (2). The row that catches people is A = 1, B = 1, where OR gives 1 but EOR gives 0; confusing the two tables is the standard error.Write out the truth table of a NAND gate, and state its relationship to the AND gate.
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A = 0 B = 0 → 1
A = 0 B = 1 → 1
A = 1 B = 0 → 1
A = 1 B = 1 → 0
NAND is AND with the output inverted, drawn with a small circle on the output (2). Every other gate can be built from NAND gates alone. Writing the AND table and forgetting to invert it is the standard error, and the give-away is the first row: NAND outputs 1 when both inputs are 0.Describe the behaviour of a D-type flip-flop.
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On each rising edge of the clock it copies whatever is on the data input D to its output Q (1), and it then holds Q frozen until the next clock edge, ignoring D completely in between (1). That is what makes it a one-bit memory; registers and computer memory are rows of them. Saying the output 'follows the input' is the standard error: it follows D only at the clock edge.State the relationship between the input and output frequencies of a chain of n toggling flip-flop stages.
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fout = fin/2n (1). Every stage halves the frequency once. Confusing this with the number of states, which is 2n rather than a division, is the standard slip.A logic circuit has output Q = (A OR B) AND NOT C. Construct its full truth table, with the inputs in binary counting order, and state how many input combinations give Q = 1.
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Three inputs give 23 = 8 rows, taken in binary order (1):
A = 0 B = 0 C = 0 → 0
A = 0 B = 0 C = 1 → 0
A = 0 B = 1 C = 0 → 1
A = 0 B = 1 C = 1 → 0
A = 1 B = 0 C = 0 → 1
A = 1 B = 0 C = 1 → 0
A = 1 B = 1 C = 0 → 1
A = 1 B = 1 C = 1 → 0
Q = 1 for 3 of the eight combinations (2). Note that C = 1 forces Q = 0 whatever A and B do, because the NOT C term feeds an AND. Writing only four rows, or listing the inputs in some order of your own, is the standard error: examiners mark the complete table in binary counting order and a missing row forfeits the mark.A chain of 10 toggling flip-flop stages is clocked at 1.024 MHz. Calculate the frequency at the output of the final stage.
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Each stage halves the frequency, so ten stages divide by 210 = 1024 (1). fout = 1.024 × 106/1024 (1) = 1000 Hz (1). Dividing by 10 rather than by 210 is the standard error, and it gives an answer a hundred times too large.A timing circuit is clocked at 2.048 MHz and must produce an output at 250 Hz. Calculate the number of toggling flip-flop stages required.
A binary counter is built from 6 toggling flip-flop stages and clocked at 4096 Hz. State the number of distinct states it passes through, the range of counts it displays, and the frequency at its final output.
A half-adder adds two single binary digits A and B. Name the gate that produces each of its two outputs, and give the sum and carry for every combination of the inputs.
An alarm sounds (Q = 1) when a door is open (D = 1) and the system is armed (R = 1) and the override key is not inserted (K = 0). Write the Boolean expression, name the gates required, and give Q for the three cases D = 1, R = 1, K = 0; D = 1, R = 1, K = 1; and D = 0, R = 1, K = 0.
A logic system uses 0 V for logic 0 and 5.0 V for logic 1, with a decision threshold at 2.5 V. A pulse sent at 4.6 V arrives with 0.9 V of noise subtracted from it. State the voltage at the receiver, and state whether the pulse is read correctly.
A pump must run (P = 1) when the tank level is low (L = 1), unless the manual stop is pressed (S = 1). It must also run whenever the test button is pressed (T = 1), whatever the other two inputs are doing. Construct the full truth table, write the Boolean expression, name the gates needed, and state how many of the eight input combinations run the pump.
A quartz watch runs from a crystal at 4 194 304 Hz. Calculate the number of toggling stages needed to produce a once-per-second tick, and calculate the frequency available at the output of the twelfth stage.
A full adder adds two bits A and B together with a carry brought in from the column to its right. It is built from two half-adders and an OR gate. Explain how the two half-adders are connected, and give the sum and carry outputs when A = 1, B = 1 and the incoming carry is 1.
A digital link uses 0 V and 5.0 V logic levels with the threshold midway. Noise accumulates at 0.35 V per kilometre of cable, and the receiver is reliable while the accumulated noise stays below 1.2 V. Calculate the greatest whole number of kilometres between regenerators, and the number of regenerators needed on a 30 km route. Explain why an analogue link over the same route cannot be rescued the same way.
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